diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h
index 0a15692..8b05757 100644
--- a/drivers/phy/marvell/comphy.h
+++ b/drivers/phy/marvell/comphy.h
@@ -86,6 +86,7 @@
 	u32 speed;
 	u32 invert;
 	bool clk_src;
+	bool end_point;
 };
 
 struct chip_serdes_phy_config {
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index 97455c8..d8877e8 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -167,6 +167,8 @@
 			blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT);
 		comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode,
 								"clk-src");
+		comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode,
+								  "end_point");
 		if (comphy_map_data[lane].type == PHY_TYPE_INVALID) {
 			printf("no phy type for lane %d, setting lane as unconnected\n",
 			       lane + 1);
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index cd3cf96..70554fe 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -87,8 +87,8 @@
 	return 0;
 }
 
-static int comphy_pcie_power_up(u32 lane, u32 pcie_width,
-				bool clk_src, void __iomem *hpipe_base,
+static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
+				bool is_end_point, void __iomem *hpipe_base,
 				void __iomem *comphy_base)
 {
 	u32 mask, data, ret = 1;
@@ -109,6 +109,7 @@
 	 * and SerDes Lane 0 got PCIe ref-clock #0
 	 */
 	debug("PCIe clock = %x\n", pcie_clk);
+	debug("PCIe RC    = %d\n", !is_end_point);
 	debug("PCIe width = %d\n", pcie_width);
 
 	/* enable PCIe by4 and by2 */
@@ -384,10 +385,12 @@
 	data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
 	reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
 
-	/* Set phy in root complex mode */
-	mask = HPIPE_CFG_PHY_RC_EP_MASK;
-	data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET;
-	reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
+	if (!is_end_point) {
+		/* Set phy in root complex mode */
+		mask = HPIPE_CFG_PHY_RC_EP_MASK;
+		data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET;
+		reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
+	}
 
 	debug("stage: Comphy power up\n");
 
@@ -1667,6 +1670,7 @@
 		case PHY_TYPE_PEX3:
 			ret = comphy_pcie_power_up(
 				lane, pcie_width, ptr_comphy_map->clk_src,
+				serdes_map->end_point,
 				hpipe_base_addr, comphy_base_addr);
 			break;
 		case PHY_TYPE_SATA0: